Workshop Program
MPP 2014 will be held in conjunction with the 26th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2014), at Paris, France. Click here to see SBAC-PAD's schedule.
October 23rd Thursday |
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08:30 08:45 |
MPP Opening Session |
08:45 09:35 |
MPP Invited Talk Elias Mizan |
09:35 10:35 |
MPP Session 1 |
10:35 11:00 |
Break |
11:00 12:00 |
MPP Keynote Michael Flynn |
12:00 13:00 |
Lunch |
13:00 14:00 |
SBAC-PAD Keynote William Blake |
14:05 16:05 |
MPP Session 2 |
16:05 16:25 |
Break |
16:25 17:25 |
MPP Keynote Arvind |
17:30 18:30 |
MPP Session 3 |
18:30 18:40 |
MPP Closing Session |
19:30 22:30 |
Banquet |
Title: Instruction Placement in a Dataflow Execution Model
Abstract: This presentation makes an overview of the instruction placement problem in dataflow engines, focusing on out-of-order processors with multiple instruction scheduler queues. It presents the differences between out-of-order and pure dataflow machines that affect the way placement is made in the two models. It then focuses on the following issues on the out-of-order model:
Abstract: This presentation makes an overview of the instruction placement problem in dataflow engines, focusing on out-of-order processors with multiple instruction scheduler queues. It presents the differences between out-of-order and pure dataflow machines that affect the way placement is made in the two models. It then focuses on the following issues on the out-of-order model:
- Should placement be made by hardware or software?
- Is code analysis useful in making an efficient placement?
- What information do we need to make an efficient placement?
- How much time do we have to make an efficient placement?
Title: Using dataflow as a high performance computing engine
Abstract:
Over the past decades parallel processor speedup has been an elusive quantity for a broad class of applications. Yet with the end of performance scaling for single processors the need for speedup has never been greater. The problem is not technology but programming models.
One answer to this is to create an idealized data flow machine that exactly corresponds to the application and stream data through the resulting machine. This two dimensional programming model is now part of the openSPL (spatial programming model) initiative. The resultant dataflow machine can be emulated with FPGAs, providing more than an order of magnitude speedup even as executed as an emulation of the data flow machine.
Abstract:
Over the past decades parallel processor speedup has been an elusive quantity for a broad class of applications. Yet with the end of performance scaling for single processors the need for speedup has never been greater. The problem is not technology but programming models.
One answer to this is to create an idealized data flow machine that exactly corresponds to the application and stream data through the resulting machine. This two dimensional programming model is now part of the openSPL (spatial programming model) initiative. The resultant dataflow machine can be emulated with FPGAs, providing more than an order of magnitude speedup even as executed as an emulation of the data flow machine.
Title: Latency-Insensitive Bounded Dataflow Graphs
Abstract:
Jack Dennis at MIT and Gilles Kahn at INRIA developed very similar dataflow models in the early 1970s though they were motivated by quite different concerns. Dennis was developing a model suitable for parallel computer architectures while Kahn was interested in parallel processes that were guaranteed to produce deterministic results. Their models were elegant partly because they abstracted away underlying resources. After working on the dataflow model for twenty years, in late nineties, I shifted to a model of guarded atomic actions (GAA) on a shared state. GAA only requires serializability of atomic actions and thus provides much weaker guarantees than traditional dataflow. Bluespec, a language based on GAAs proved to be very useful in describing and synthesizing both hardware and software. A decade later I was able to combine the two models by using dataflow to impose high-level structure on computations described using GAAs. I call this model Latency-Insensitive Bounded Dataflow Graphs (LI BDNs) and will illustrate its use in Hardware-Software co-design and in cycle-accurate simulation of multicores on FPGAs.
Abstract:
Jack Dennis at MIT and Gilles Kahn at INRIA developed very similar dataflow models in the early 1970s though they were motivated by quite different concerns. Dennis was developing a model suitable for parallel computer architectures while Kahn was interested in parallel processes that were guaranteed to produce deterministic results. Their models were elegant partly because they abstracted away underlying resources. After working on the dataflow model for twenty years, in late nineties, I shifted to a model of guarded atomic actions (GAA) on a shared state. GAA only requires serializability of atomic actions and thus provides much weaker guarantees than traditional dataflow. Bluespec, a language based on GAAs proved to be very useful in describing and synthesizing both hardware and software. A decade later I was able to combine the two models by using dataflow to impose high-level structure on computations described using GAAs. I call this model Latency-Insensitive Bounded Dataflow Graphs (LI BDNs) and will illustrate its use in Hardware-Software co-design and in cycle-accurate simulation of multicores on FPGAs.
- An Introduction to DF-Threads and their Execution Model
Roberto Giorgi (University of Siena, Italy)
-Dataflow Virtual Machine Profiling
Vittor F. Lira, Felippe H. Cerreia (UERJ, Brazil),
Leandro Santiago (UERJ, Brazil),
Alexandre C. Sena (UERJ, Brazil),
Maria Clicia S. de Castro (UERJ, Brazil),
Leandro A. J. Marzulo (UERJ, Brazil)
Roberto Giorgi (University of Siena, Italy)
-Dataflow Virtual Machine Profiling
Vittor F. Lira, Felippe H. Cerreia (UERJ, Brazil),
Leandro Santiago (UERJ, Brazil),
Alexandre C. Sena (UERJ, Brazil),
Maria Clicia S. de Castro (UERJ, Brazil),
Leandro A. J. Marzulo (UERJ, Brazil)
- High-Level Dataflow Programming for Reconfigurable Computing
Jocelyn Serot (Université Blaise Pascal, France),
Francois Berry (Université Blaise Pascal, France)
- Stack-Tagged Dataflow
Leandro Santiago (UERJ, Brazil),
Leandro A. J. Marzulo (UERJ, Brazil),
Bruno F. Goldstein (UFRJ, Brazil),
Tiago A. O. Alves (UFRJ, Brazil),
Felipe M. G. França (UFRJ, Brazil)
- Stream Oriented Modular Architecture with Polymorphic Processing Engines
Andriy Gorobets (Universidade de Lisboa, Portugal),
Frederico Pratas (Imagination Technologies, Portugal),
Nuno Roma (Universidade de Lisboa, Portugal),
Pedro Tomás (Universidade de Lisboa, Portugal)
- The ChipCflow: a tool to generate hardware accelerators using a static dataflow machine designed for a FPGA
Antonio Carlos Fernandes da Silva (UTFPR, Brazil),
Jorge Silva (USP, Brazil)
Jocelyn Serot (Université Blaise Pascal, France),
Francois Berry (Université Blaise Pascal, France)
- Stack-Tagged Dataflow
Leandro Santiago (UERJ, Brazil),
Leandro A. J. Marzulo (UERJ, Brazil),
Bruno F. Goldstein (UFRJ, Brazil),
Tiago A. O. Alves (UFRJ, Brazil),
Felipe M. G. França (UFRJ, Brazil)
- Stream Oriented Modular Architecture with Polymorphic Processing Engines
Andriy Gorobets (Universidade de Lisboa, Portugal),
Frederico Pratas (Imagination Technologies, Portugal),
Nuno Roma (Universidade de Lisboa, Portugal),
Pedro Tomás (Universidade de Lisboa, Portugal)
- The ChipCflow: a tool to generate hardware accelerators using a static dataflow machine designed for a FPGA
Antonio Carlos Fernandes da Silva (UTFPR, Brazil),
Jorge Silva (USP, Brazil)
- A Minimalistic Dataflow Programming Library for Python
Tiago A. O. Alves (UFRJ, Brazil),
Brunno F. Goldstein (UFRJ, Brazil),
Leandro A. J. Marzulo (UERJ, Brazil)
Felipe M. G. França(UFRJ, Brazil)
- Scheduling of Recursive and Dynamic Data-Flow Graphs using Stream Rewriting
Lars Middendorf (University of Rostock, Germany),
Christian Haubelt (University of Rostock, Germany)
Tiago A. O. Alves (UFRJ, Brazil),
Brunno F. Goldstein (UFRJ, Brazil),
Leandro A. J. Marzulo (UERJ, Brazil)
Felipe M. G. França(UFRJ, Brazil)
- Scheduling of Recursive and Dynamic Data-Flow Graphs using Stream Rewriting
Lars Middendorf (University of Rostock, Germany),
Christian Haubelt (University of Rostock, Germany)
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